yesterday i searched for some of the parts and put the 68008 on the bread board. According to other projects it is possible to do a "free run" by pulling all data lines to low. Though some people say it's the opcode of NOP it actually is some kind of ORI.
I wanted to check some prerequisites of the project:
- Does the CPU work?
- Can !DTACK (data acknowledge) be held permanently low?
- Can !VPA (valid peripheral address) be used for instruction fetch cycle?
ad 2: Yes, as i could tell the CPU works. :-)
ad 3: For curiosity: Yes. I believe that bus cycles and internal logic are completely separated and !VPA can be used for any bus cycle.
Next interesting question: Can i put videos in my blog? It seems i can, but for a final verification i probably have to publish this page.
Update: They are just converted into poor animated GIFs. I'll have to find something better... ok, uploaded them to youtube and embedded. back to the roots...
|Free Run using !DTACK-terminated bus cycles|
An important result is that the 68008 actually works without deactivating !DTACK after each bus cycle. Though in all timing diagrams bus cycles start with !DTACK high it is actually possible to keep it low the whole time.
|Free Run using !VPA-terminated bus cycles|
Actually the M68000 8-/16-/32-Bit Microprocessors User’s Manual Ninth Edition says 10 to 19 cycles, while the M68000 Family Reference Manual – MC68008 Technical Summary says 11 to 18 cycles.
|Buggy timing diagram for the 'best case' !VPA-terminated bus cycle|
In the second video one bus cycle takes 10 clock cycles instead of 4 and therefore A19 should blink with 2 Hz *4 / 10 = 0.8 Hz instead. I think this approximately true.
In my project the !VPA bus cycle is used to access slow peripherals on the K1 bus. But it is also used during interrupt acknowledge, in order to use an auto vectored interrupt. Now the interesting question is: Does the CPU actually perform a !VPA controlled bus cycle here or a dummy cycle, as it ignores the byte read?
|!VPA used in interrupt vector read cycle|
The bus interface performs a slow memory cycle in the (dummy) interrupt vector read cycle if !VPA is activated to request an auto vector interrupt.