Debugging the LCD Display Driver and Hardware

This week i worked on the 640x480 pixel b&w LCD terminal.  Soldering was easy, but fixing all the bugs took some time. I also had  to do some changes to the terminal code because i realized that i was using the LCD upside down.

I connected the LCD and powered the board through the programming  header. Off course nothing worked, except for the display refresh routine, which brought up a picture of the erased DRAM cells. Step by  step i brought up more functions: Erase screen, print characters, read  and write whole pixel lines and scrolling. I had to add some nops to the DRAM read and write timing, because the data goes through series resistors which create some delay. For the next board i'll reduce them slightly. Then printing of standard-size characters with 4 attributes in all combinations works.

 Finally one last important step: Attach it via serial line to USB to my Mac. Nothing worked. I adjusted the Baudrate on both sides. I printed text from the LCD terminal on the serial line in an endless loop. There was no signal on the TxD line. Why? But there seemed to be a signal on the RxD handshake line. ... ???

I had connected data lines to handshake and handshake to data lines on the board. :-(. Fixed it with a cutter, solder and wire. Tested. Worked. :-)


Debugging i2c

And on it goes. The last days i spent finding out, why the i2c interface did not work. Hardware is ok, it's a problem with the software. First i thought, all i2c eeproms have a block size of 64 bytes. But that's not that easy. Block size varies with eeprom size. And manufacturer… :-| But most 8k eeproms have blocks of 32 bytes and most 16k and 32k eeproms have blocks of 64 bytes.

Then busy polling after a block write did not work properly. I started a read cycle to detect the busy state (the eeprom does not respond if busy) but this behaviour is only defined if you start a write cycle. So i rewrote my source to do this.

Then somehow my start and stop sequences on the i2c bus sometimes failed. Now i test-read the data line to see if it is high and not pulled low by the target, for whatever reason.

Now access to the K1 bus eeproms works properly and hopefully reliably. I successfully downloaded the SIO driver code into the SIO driver eeprom and booted the CPU with driver initialization from eeproms, and not with data from the microcode. And it works! :-)

And, last not least, selecting the i2c eeprom on a K1 bus card works as planned: All eeproms are addressed with address 0b000, but only the eeprom on the currently selected extension card actually has this address. The i/o cards disable their eeprom while they are not selected, and the easiest way to do this is to set any address pin of the eeprom to '1', so that the address does not match.


Debugging the SIO board

Instead of writing some 'useful' commands i spend the last days tracking down a weird error. When i activated the timer interrupt of the 88C192 UART to give me a system timer interrupt of 100 Hz, the whole system got stuck. The simulator worked, the real hardware stalled. Bad!

It took me some time with the minimalistic debugging facilities to come to the conclusion, that the interrupt does not go away. When i rewrote the RETI (return-from-interrupt) opcode to execute the next  opcode regardless of interrupt state the system made it to the shell prompt, though eating all the cpu power. This only happened when i enabled the timer interrupt, else everything seemed to be ok. I double checked my code three times. Have i a broken UART? Is the documentation wrong?
Finally, when i programmed the UART to the longest possible duration, this left ~90% cpu time in the 'Halt' state (at 8MHz). Some observations later i discovered, that interrupts came in bursts. I measured the burst rate: ~3.5Hz. I did a calculation of the interrupt frequency: 7.372MHz/32/0xFFFF = 3.515Hz. This proved, that the timer interrupt generated the bursts.

But why did the interrupt stay active for ~1/35 sec (given the 10% cpu usage) and then go away? I examined my circuit design very carefully ... VERY carefully ... this whole thing looke like a ... and there i got it: The /INT output of the UART is open collector and i had no pull-up resistor fitted there! Now all observations made sense. I soldered a 5kΩ resistor between 2 suiting pins, restored the SIO eeprom driver, compiled the microcode rom, uploaded it to the front panel, resetted the cpu from the front panel eeproms and yepp, it worked! :-) The timer interrupt now eats approx. 1% (at 8MHz).


Debugging the CPU


I'm now moving back from emulation to the real hardware. I expected problems, and there they are.
Somehow upload of microcode files to the front panel did not work. First it hangs with XOFF, so i disable XON/XOFF and lower the baud rate. Then it transfers up to address 0x4A00 and aborts with an error. Each time i try to do 'something' to find out the cause the error changes. Finally i find out that at that position is the first unused gap in the microcode and obviously refresehing the LCD is so time consuming that even the longest delay after one line of code (100ms) is not enough. Strange, when i re-enabled XON/XOFF it worked. So microcode upload to the CPU is working again.
Fundamental Timing of the K1-16/16 CPU
Now the code does not make it beyond the initial register test. Loading the SR (shift-right) register failed to load the CY input to data bit D15. I remember that there was a problem with exactly this when i tested it more than one year ago. I had settled my mind it was a contact issue and tried to prove this now again. But it isn't. Actually the little chart with the fundamental timing of the CPU contains the secret:
The blue clk is the load signal for the registers – SR is a register – and the rising edge is where it latches new data from the data bus and, in case of data bit D15, from the CY line. The CY line is a 'option control' line, it controls options in the various registers, if they have. As can be seen in the image the option control line toggles exactly at the same moment (if it toggles) when the clk line raises. So we have a race condition here.
The only thing i can do is to delay the CY option control line for the shift registers. I examined whether this problem will show up at other places too, but it seems not. Whereever CY (or any other option control line) is used, there are some gate delays between the option control line and the data latching register. So it's enough to delay this signal for SR and SL only. Luckily there is an unused OR gate on the data registers board which i will use for this.


All test code performed without error. :-) Except for i2c test, because i have not yet attached any io device.


Weekend … phantastic weather … what to do? ok, i manufactured the K1-system-bus. ;-)


Tata! The SIO board works. Today i got the console prompt on the terminal. There are still some issues to examine: Speaking to the i2c eeprom did not work. The hardware seems to work properly, but the eeprom does not respond. This is to be investigated. Whether interrupts work as expected is still to be tested. Though they seem to work.


Yep. Interrupts obviously work. SIO works: i/o to serial to my Mac works and i/o to the front panel works. Now i'll have to add some extras to the terminal in the frontpanel, e.g. handle some control codes. ;-) And then add some stuff to the boot shell of the computer, like cd, ls and so on. And investigate the i2c problem.