After a long while I resumed work on the Arithmetic/Logic Unit. I wired
up a test circuit for the 3-resistor majority gate, which i use in the
ALU for the joined AND and OR functions. I was lucky and the gate worked
as expected. Dieter Müller has written an
article about the majority gate and it's use for ALU design.
Website now offline (2010) and email address invalid. I don't know what has happened to him :-/
