Working on microcode

Working on the microcode and microcode assembler.The microcode is organized in 2 planes of 16k * 24-bit codes. There is a 1-instruction pipeline which imposes a 1-instruction latency on code branching: In every microcode instruction a flag is selected. This flag is tested at the end of the previous instruction and determines from which code plane the next instruction is read. The assembler takes care for the most of this brain hazzard.