68008 SRAM Microcomputer – Unused 2-to-4 Line Decoder Got a Job!

browsing through some other 68008 projects in the web

• daveho.github.io (unfinished)
• wandel.ca (documentation of older project)
• kiwi that's a really adorable project!

i was reminded to the fact, that the 68000 has something called short addressing: Instead of supplying a 4-byte long address you only supply a 2-byte short address which is sign-extended to 4 bytes. This saves space in program code and – more important – up to 8 CPU clock cycles. So i took a look at my current address layout:

v0.2 address decoder

This allows the first 32k of RAM to be accessed with short addressing as well as the slow I/O address range, but not the fast I/O range:

• %xxxxxxxx,xxxx00xx,xxxxxxxx,xxxxxxxx selects RAM and
  %00000000,00000000,0xxxxxxx,xxxxxxxx is a possible subset of this which fit's in a signed word.
• %xxxxxxxx,xxxx01xx,xxxxxxxx,xxxxxxxx selects ROM and can never be accessed with short addressing.
• %xxxxxxxx,xxxx11xx,xxxxxxxx,xxxxxxxx selects slow I/O and
  %11111111,11111111,1xxxxxxx,xxxxxxxx is a possible subset of this which fit's in a signed word as a negative value.
• %xxxxxxxx,xxxx10xx,xxxxxxxx,xxxxxxxx selects fast I/O and can never be accessed with short addressing.

In order to make all I/O short addressable, all I/O must have A31 .. A15 high. A18 cannot be used to select between slow and fast I/O. The first Address line which can be used for that is A14:

v0.3 address decoder

Now the memory map is as follows:

• %xxxxxxxx,xxxx00xx,xxxxxxxx,xxxxxxxx selects RAM and
  %00000000,00000000,0xxxxxxx,xxxxxxxx is a short addressable subset.
• %xxxxxxxx,xxxx01xx,xxxxxxxx,xxxxxxxx selects ROM (no short addressable subset).
• %xxxxxxxx,xxxx1xxx,x1xxxxxx,xxxxxxxx selects slow I/O and
  %11111111,11111111,11xxxxxx,xxxxxxxx is a short addressable subset.
• %xxxxxxxx,xxxx1xxx,x0xxxxxx,xxxxxxxx selects fast I/O and
  %11111111,11111111,10xxxxxx,xxxxxxxx is a short addressable subset.

There is no need to apply the post-reset INIT line pull-up to A14 for the I/O address decoder and there is no need to strobe the outputs with !AS because the I/O control lines are strobed by !AS directly at the 74HC138 which generates them (see other sheet – next to come :-)). It's even better this way because now !SLOW_IO which is directly connected to the CPU's !VPA input to request slow I/O or an auto vector toggles before !AS is valid and not shortly thereafter.

Funny Note

Actually this second 2-to-4 line decoder could be replaced entirely by one NAND gate: !FAST_IO is not used anywhere (actually it is currently used to reset the INIT line, but this could have been !SLOW_IO as well) and !SLOW_IO becomes low when A14 and A19 are both high, so, yes, that's a NAND function. The NAND gate would even be faster (the 74HCT139 is pretty slow) but – i don't have a spare NAND gate, but i had a spare 2-to-4 line decoder. :-)